Fintronic Super FinSim v9.3.51
FintronicSuperFinSimv9.3.51英文正式版(線性FinSimVerilog仿真器軟體)
破解說明:
checkcrack\install.txt
內容說明:
Super-FinSim是頂級的線性FinSimVerilog仿真器，從1993年放出第一款FinSimVerilog
仿真器至今，FinSimVerilog已經引入了許多嶄新的功能：混合編譯和解釋型仿真，仿真
工廠可以讓工程師管理數以百計的同步仿真、分離和增量編譯、高性能保存和重啟、
直接集成C代碼，無須PLI。
英文說明:
Super-FinSimisthetopofthelineFinSimVerilog
simulator.EversincethefirstFinSimVerilogsimulatorhas
beensoldin1993,theFinSimVerilogsimulatorshave
introducedmanynewfeaturesthathavebecomestateofthe
artinVerilogsimulation:mixedCompiledandInterpreted
simulation,simulationFarmthatallowsoneengineerto
managehundredsofsimultaneoussimulations,separateand
incrementalcompilation,highperformancesaveandrestart,
directintegrationwithCcodewithouttheneedforPLI,
etc.SuperFinSimsupportstheentireVerilogstandardIEEE
1364-1995andmanyfeaturesofIEEE1364-2001,whichare
listedunderSupportforVerilog2001.It'ssupportincludes
SDF,VCD,PLI,aswellasexcellentintegrationwithother
toolssuchasatightintegrationviaAPI(forbetter
performancethanPLIintegration)withDebussyandVerdi
debugenvironmentsfromNovasSoftware,andexcellentPLI
integrationswithSpecmanfromVerisityandVerafrom
Synopsysfortestbenches,MMAVfromDenaliformemory
models,UndertowfromVeritoolsfordebugenvironment,
HDLScorefromSummitDesignforcodecoverage,and
others.IntheDASolutionLimited`96benchmark,the
predecessorofSuper-FinSim,FinSim-ECS,wasratedthe
fastestVerilogsimulator.FinSimwasratedthefastest
PC-basedVerilogsimulatorintheASIC&EDAbenchmark.
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